1. Field of the Invention
The present invention relates to a semiconductor device such as a DRAM (Dynamic Random Access Memory), and more particularly to a semiconductor device having an N-type well structure.
2. Description of the Related Art
A representative example of a related art semiconductor device having a triple-well structure is illustrated in FIG. 1. Typically, this semiconductor device has a three-layered structure in which N-type embedded layer 6 is provided on P-type silicon substrate 1 that is manufactured in a CZ method (Czochralski method) and contains boron having a concentration of about 1E+15 atom/cm3 and oxygen having a concentration of about 1E+18 atom/cm3, and P-type well (P-well) 3 is further formed thereon. The N-type embedded layer 6 includes two layers of N-well 5 that is deeper than shallow trench isolation (STI) region 2 and Deep-N well 4 that is further deeper than the STI region. This triple-well structure is so featured that NMOS1 forming region of FIG. 1 is covered with the P-well 3, the periphery thereof is covered with the N-well 5 and the Deep-N well 4, and the P-well 3 is formed independently of the P-type silicon substrate 1. Accordingly, in the DRAM, if a transistor of a memory cell portion is formed in NMOS1 forming region, different substrate potentials can be taken from an NMOS (NMOS2) of a peripheral circuit portion and an NMOS of the memory cell portion, and voltage designs of the transistors of the peripheral circuit portion and the memory cell portion can be independently optimized. Further, since the transistor of the memory cell portion is electrically insulated from other elements, noise from the other elements can be blocked. For example, since carriers generated from the peripheral circuit cannot intrude a transistor region of the memory cell portion, data that is maintained in a capacitor connected to the transistor of the memory cell portion is not destroyed. In FIG. 1, numerous signs 7, 8 and 9 denote a gate insulating film, a gate electrode, and a source/drain, respectively. Further, the Deep-N well or the N-well is formed by injecting N-type impurities into a place that is about several microns deep from the surface of the substrate by high-energy ion injection (for example, see FIG. 6).
In a highly integrated device such as a DRAM, electrical insulation (isolation voltage) between the N-type embedded layer 6 and the P-type silicon substrate 1 or between the respective N-type embedded layers 6 as illustrated in FIG. 1 becomes important for device performance. FIG. 2 is a cross-sectional view of a representative DRAM cell transistor portion. For a peripheral circuit portion except for a cell transistor, a general COMS process is used. Here, a well structure related to the present invention will be described using the DRAM cell transistor structure illustrated in FIG. 2. First, a P-type silicon wafer is prepared as P-type semiconductor substrate 21. An active region is surrounded by STI region 22 in which an insulating film is buried, and p-type well 23 to which at least the substrate potential is given and a p-type doped channel layer which determines a threshold voltage of the transistor are formed on the active region. Here, an N-type embedded well layer (Deep-N well) 24 is formed on a lower portion of the p-type well to cover the STI region 22 and all cell transistors. Further, although not illustrated in the drawing, in a region where the Deep-N well 24 is formed, a circuit for sensing data of the cell transistor is mounted in addition to the cell transistor. Further, two gate electrodes 27 are formed on both sides of plug 26 that is connected to DRAM bit line 25, gate insulating film 28 is formed between the gate electrode 27 and the p-type doped channel layer, and side spacers 29 are formed between the gate electrode 27 and the plug 26. In the active region in which the gate electrode 27 is not formed, N-type impurity diffusion layers 30 (LDD) and 31, which become a source and a drain, are formed. The N-type impurity diffusion layers 30 and 31 are in contact with plugs 32 that are connected to a capacitor in addition to the plug 26 connected to the bit line 25. Interlayer insulating film 33 is formed between the plugs. Interlayer insulating film 34 is formed between the plugs 26 and 32 and the bit line 25, and interlayer insulating film 36 is formed between the bit line 25 and capacitor 35. On the capacitor 35, first Al film 37 and second Al film 38 are formed intervening interlayer insulating film 39 as wiring layers. Further, interlayer insulating film 40 is formed between the both Al films. Plasma oxide film 41 is formed on the second Al film of an upper layer as a cover film. Thereafter, in order to hydrogen-terminate the interface state of a gate oxide film interface of the transistor MOS and an STI interface, hydrogen alloying is performed.
The DRAM semiconductor device as described above has several problems. Typically, a CZ substrate contains interstitial oxygen of about 1E+18 atom/cm3. Since the interstitial oxygen has excessive concentration which is higher than the concentration that can be solubilized at a typical DRAM heat treatment temperature, oxygen cluster (oxygen donor) or oxygen precipitation nuclei (SiOx) is formed through the heat treatment. In a prolonged heat treatment at about 400° C. to 500° C., it is known that the interstitial oxygen is aggregated to act as a donor impurity. For example, if oxygen donors appear through aggregation of oxygen in a boron-doped P-type silicon wafer, the substrate resistance becomes high, and thus carrier electron concentration that is caused by the oxygen donors becomes high in comparison to the amount of boron doping to cause the P-type to be reversed to the N-type. In a highly integrated DRAM for low power consumption, since an excessive heat load that is caused by high-temperature heat treatment is avoided with the miniaturization of transistors, the total processing time for low-temperature heat treatment (400° C. to 500° C.) that causes the generation of the oxygen donors becomes more, and thus the above-described problem becomes severer. FIG. 3A shows the deterioration of well breakdown voltage that is caused by the high resistance of the inside of substrate 51 through generation of the oxygen donors. Since a portion that is deeper than the region of P-type well 53 has high resistance due to low boron concentration, depletion layer 55 is expanded to be connected between adjacent N-wells (Deep-N well 52 and N well 54), and thus leak current (indicated by an arrow) flows therethrough. Further, as illustrated in FIG. 3B, oxygen precipitation nuclei 56 that is generated in the high-temperature process acts as a generation-recombination center if the oxygen precipitation nuclei are present in the depletion layer 55 of a PN junction, and thus abnormal current leakage occurs to cause deterioration of the device characteristics. That is, in the PN junction between the N well and P substrate, which needs to be formed deep in the substrate, the possibility that the oxygen precipitation nuclei are included in the depletion layer is increased. If the current leakage is increased, the power consumption is also increased, and in the worst case, the breakdown voltage between adjacent N wells is lowered to cause device malfunction. Accordingly, in order to prevent the device malfunction by the current leakage between the wells, (1) control of the amount of oxygen donor (and control of boron distribution) that is generated in dependence upon the oxygen concentration in a region below the well and (2) control of the depth of the top surface of the oxygen precipitation nuclei are required. FIG. 4 shows the result in that the breakdown voltage between adjacent N wells has been changed by low-temperature heat treatment conditions A-C (at 450° C.) that influence the amount of oxygen donor generation and an oxygen concentration condition just below the N well in the case where a DRAM has been actually manufactured. Further, the boron concentration just below the N well is about 1E+15 atom/cm3. As can be seen from the result, as the oxygen concentration just below the N well becomes higher and the heat treatment time at 450° C. becomes longer, the N well breakdown voltage becomes lowered. Further, the shallowest depth of oxygen precipitation nuclei in this experiment is 4 to 5 μm from the substrate surface.
As described above, since the oxygen concentration distribution of the device active region near the substrate surface exerts a bad influence on the device characteristics, there is a method in which an epitaxial silicon layer (hereinafter may be referred to as an “Epi-layer”) is thickly provided on the CZ substrate surface as a defect-free layer. However, if the Epi-layer is equal to or thicker than 3 μm, the Epi-layer is formed to be thickly crowded around the rear surface side of the wafer edge, and thus the flatness in the periphery of the wafer is deteriorated. The deterioration of the flatness in the periphery of the wafer causes strict uniformity of the exposure amount in the surface during pattern exposure in manufacturing the current miniaturized device, and thus the good acquisition rate is decreased in the periphery of the wafer. Accordingly, there is a need to solve the above-described problem through the Epi-layer of 3 μm or less. As the Epi-layer becomes thick, the wafer cost is increased. On the other hand, there has been an attempt to reduce the generation amount of oxygen donor or oxygen precipitation nuclei through lowering of the oxygen concentration in the substrate without the Epi-layer or with a thin Epi-layer. Since the oxygen precipitation nuclei in the substrate bring so-called gettering effect for capturing heavy metal contaminants mixed in the device manufacturing process, a certain amount of oxygen precipitation nuclei is needed inside the substrate. Further, COP (Crystal Originating Particles), of which the generation amount is changed by wafer raising conditions, or stacking faults are present in the CZ substrate in addition to the oxygen donors or oxygen precipitation nuclei, and if the CZ substrate is used without the Epi-layer, problems in that the device yield is deteriorated due to the above-described faults have to be solved.